Reminder: Submission must be on time as discussed in class.
Where the solution requires a process, show that process, not simply the
solution. Your grade in all the homework assignments and exams depends on the
legibility of submission: typing or screen shots preferred, ensuring that page
arrangement is all the same direction orientation.
1. (2.5 points)
Majority rules. Some systems designed, like processing in our brains, require
voting inputs to determine output. A majority function produces an output value
of 1 if there are more 1’s than 0’s of its inputs. Design a 3-input majority
function. Give the simplest possible algebraic function and circuit logic,
using only OR and AND gates to implement.
2. (2.5 points)
Traffic Light Sequential Design. Traffic light control at a simple ‘+’
intersection uses a binary counter to produce the following sequence of
combinations on input lines A, B, C and D: 0000, 0001, 0011, 0010, 0110, 0111,
0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000. The sequence
continues from the beginning with the next code, 0000. Each combination is
applied for 5 seconds, then cycles to the next. These inputs drive
combinational logic for six outputs to light lamps as follows:
–
Red-north/south (RNS)
–
Yellow-north/south (YNS)
–
Green-north/south (GNS)
–
Red-east/west (REW)
–
Yellow- east/west (YEW)
–
Green- east/west (GEW)
Each lamp is controlled by its respective output: turned ON
for a logic 1 applied and OFF for a 0. Given an entire sequence of 80 seconds,
split into 16 five-second intervals, for each direction, its green is on for 30
seconds, yellow for 5 seconds, and red for 45 seconds. (Red intervals overlap 5
seconds for safety.) As the 16 combinations sequence, determine lamps that
should be lit in each interval to cause the desired driver behavior. Given
starting conditions at beginning of interval 0000 set GNS = 1 and REW = 1 with
all other outputs are 0: design the logic to produce the six outputs using AND
and OR gates and inverters.
3. (2.5 points)
Metering lights. In order to speed up an autobahn, a traffic metering system is
under design to release traffic from the entrance ramp onto the highway. Three
lanes in parallel approach the metering lights, each with its own stop (red) –
go (green) pair of lights. One lane, designated for car pools, is given
priority for a green light over the other two lanes, distinguished as left and
right. Otherwise, a “round robin” scheme in which the green lights alternate is
used (for left and right lanes). Design the control module logic to drive each
light (GREEN = 1; RED = 0) given these specifications:
Inputs:
–
PS Car pool lane sensor (car present = 1; car absent = 0)
–
LS Left lane sensor (car present = 1; car absent = 0)
–
RS Right lane sensor (car present = 1; car absent = 0)
–
RR Round robin signal (select left = 1; select right = 0)
Outputs:
–
PL Car pool lane light (GREEN = 1; RED = 0)
–
LL Left lane light (GREEN = 1; RED = 0)
–
RL Right lane light (GREEN = 1; RED = 0)
Operation:
1) If there is a car
in the car pool lane, PL = 1.
2) If there are no
cars in the car pool lane and right lane, but there is a car in the left lane,
LL = 1.
3) If there are no cars in the car pool lane and left lane,
but there is a car in the right lane, RL = 1.
4) If there are no cars in the car pool lane and cars in
both left and right lanes,
i. If RR = 1, then LL = 1.
ii. If RR = 0, then RL = 1.
5) If any PL, LL, or RL is not specified to be 1 above, then
it is cleared to value 0.
a) Find the truth table for the control module logic.
b) Find a minimum multiple-level gate implementation with
minimum gate-input cost using AND and OR gates and inverters.
4. (2.5 points) Design an 8- Input NAND gate. For each of
the following cases, minimize the number of gates used in the multiple-level
result:
a) Design an 8- Input NAND gate using 2- Input NAND gates
and inverters (NOT gates).
b) Design an 8- Input NAND gate using 2- Input NAND gates,2
– Input NOR gates, and inverters (NOT gates) only if needed.
c) Compare the number of gates used in a) and b).
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